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Disambiguation of "Kim, Tony Tae-Hyoung"

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Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2165-2173 (2016)

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Hyoung-Gook Kim

Moo-Hyoung Kim

Hyoung Seok Kim

Hyoung-Soo Kim

Tae-hy Kim

 

Other publications of authors with the same name

Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement., and . ISOCC, page 163-166. IEEE, (2011)0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance., , , , , and . IEEE J. Solid State Circuits, 49 (7): 1487-1498 (2014)A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (10): 1707-1719 (2021)Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2165-2173 (2016)A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 340-352 (January 2023)Guest Editorial Special Issue on Selected Papers From ISCAS 2021., , and . IEEE Trans. Biomed. Circuits Syst., 15 (6): 1126-1128 (2021)A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance., , and . Microelectron. J., (2017)A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications., , , and . IEEE Open J. Circuits Syst., (2021)On-chip reliability monitors for measuring circuit degradation., , , and . Microelectron. Reliab., 50 (8): 1039-1053 (2010)An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (6): 947-956 (2010)