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Disambiguation of "Patil, Sharvil"

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Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time.

, , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1514-1524 (2016)

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Pratap Patil

Nanoscopic metal fluoride based novel solid catalysts. HU Berlin, (2008)

Manohar Patil

Ganesh Patil

Nitin Patil

Naishadh Patil

 

Other publications of authors with the same name

A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4731-4740 (2022)Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time"., , , , , , , and . IEEE J. Solid State Circuits, 53 (6): 1870 (2018)Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (3): 1017-1030 (2019)22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors., , , , , , , , , and 3 other author(s). ISSCC, page 390-392. IEEE, (2024)Improved Implementation of CRL and SCRL Gates for Ultra Low Power., , and . ARTCom, page 123-125. IEEE Computer Society, (2009)A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD., , , , , , , , and . IEEE J. Solid State Circuits, 52 (12): 3219-3234 (2017)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter., , , , , , , , , and 5 other author(s). ISSCC, page 260-262. IEEE, (2020)Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time., , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1514-1524 (2016)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)