( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver.

, , , и . IEEE J. Solid State Circuits, 40 (9): 1909-1921 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Laurence Victor Vito

Vito Giustiniani

Vito Pinto

Vito Stancanelli

Vito Roberto

 

Другие публикации лиц с тем же именем

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers., , , , , , , , и . IEEE J. Solid State Circuits, 41 (2): 339-351 (2006)Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors., , и . ESSCIRC, стр. 501-504. IEEE, (2003)Low-power pipeline ADC for wireless LANs., , , , , , и . IEEE J. Solid State Circuits, 39 (8): 1338-1340 (2004)A "divide and conquer" technique for implementing wide dynamic range continuous-time filters., , , и . IEEE J. Solid State Circuits, 39 (2): 297-307 (2004)High-Performance CMOS TIA for Data Center Optical Interconnects., , , , , , и . BCICTS, стр. 9-16. IEEE, (2022)A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links., , , , , , и . IEEE J. Solid State Circuits, 54 (11): 3180-3190 (2019)Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion., , , , , и . IEEE J. Solid State Circuits, 37 (8): 1003-1011 (2002)Stable high-order delta-sigma digital-to-analog converters., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 200-205 (2004)Nonlinearity correction for multibit ΔΣ DACs., , , , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1033-1041 (2005)A power efficient channel selection filter/coarse AGC with no range switching transients., , и . CICC, стр. 21-24. IEEE, (2003)