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Disambiguation of "Pattanaik, Manisha"

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Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications

. IJACSA - International Journal of Advanced Computer Science and Applications, 2 (5): 43--49 (2011)

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Manisha Pujari

Manisha Jain

Manisha Juneja

 

Other publications of authors with the same name

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology., , , , and . Circuits and Systems, 2 (4): 326-329 (2011)Operation-aware assist circuit design for improved write performance of FinFET based SRAM., , , and . VDAT, page 1-6. IEEE, (2014)A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate., , and . ISED, page 151-153. IEEE, (2012)Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits., and . J. Low Power Electron., 10 (1): 45-52 (2014)A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design., and . CSSP, 37 (2): 475-499 (2018)An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\) 32-bit Register File., and . CSSP, 36 (12): 4789-4808 (2017)High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell., , and . Wireless Personal Communications, 78 (1): 57-68 (2014)Novel Ultra Low Leakage FinFET Based SRAM Cell., , and . iNIS, page 89-92. IEEE, (2016)Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology., , and . iNIS, page 234-237. IEEE, (2017)An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture., , , and . VLSID, page 133-138. IEEE, (2023)