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Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.

, , , , , , , and . ICCAD, page 1-6. IEEE, (2021)

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Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm., , , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning., , and . CoRR, (2021)Stream Processors: Progammability and Efficiency., , , , and . ACM Queue, 2 (1): 52-62 (2004)AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies., , , , , , , , , and . ISPD, page 175-183. ACM, (2022)Accelerating Chip Design with Machine Learning.. MLCAD, page 33. ACM, (2020)From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus., , , , and . ICPP, page 88:1-88:12. ACM, (2022)FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning., , , , , , , , , and . ASP-DAC, page 19-25. IEEE, (2020)GPU design in a power-limited era.. MSE, page 68. IEEE Computer Society, (2013)