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Disambiguation of "Katoh, Kentaroh"

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Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.

, , , , , , and . J. Electron. Test., 31 (4): 419 (2015)

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Eishow Katoh

Eishow Katoh

Marcus Katoh

Eishow Katoh

 

Other publications of authors with the same name

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths., , and . IEICE Trans. Inf. Syst., 92-D (3): 433-442 (2009)Design for Delay Fault Testability of 2-Rail Logic Circuits., , and . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators., , , , , and . Asian Test Symposium, page 140-146. IEEE Computer Society, (2013)A Delay Measurement Technique Using Signature Registers., , , , and . Asian Test Symposium, page 157-162. IEEE Computer Society, (2009)Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2008)A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator., , , , , , and . J. Electron. Test., 30 (6): 653-663 (2014)Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing., , , , , , , , , and 3 other author(s). IEICE Electron. Express, 20 (1): 20220470 (2023)A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation., , , , , , , , , and 3 other author(s). ITC-Asia, page 1-6. IEEE, (2023)Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability., , and . DFT, page 31-40. IEEE Computer Society, (2007)An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (5): 804-817 (2012)