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Design for Delay Fault Testability of 2-Rail Logic Circuits., , и . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths., , и . IEICE Trans. Inf. Syst., 92-D (3): 433-442 (2009)A Delay Measurement Technique Using Signature Registers., , , , и . Asian Test Symposium, стр. 157-162. IEEE Computer Society, (2009)An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators., , , , , и . Asian Test Symposium, стр. 140-146. IEEE Computer Society, (2013)Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing., , , , , , , , , и 3 other автор(ы). IEICE Electron. Express, 20 (1): 20220470 (2023)Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability., , и . IPSJ Trans. Syst. LSI Des. Methodol., (2008)A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator., , , , , , и . J. Electron. Test., 30 (6): 653-663 (2014)A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation., , , , , , , , , и 3 other автор(ы). ITC-Asia, стр. 1-6. IEEE, (2023)Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability., , и . DFT, стр. 31-40. IEEE Computer Society, (2007)An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection., , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (5): 804-817 (2012)