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An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.

, , , , , , , , , и . ESSCIRC, стр. 426-429. IEEE, (2008)

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Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition discharges. Uni Saarbrücken, (2009)

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Stéphane Jean

 

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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application., , , , и . IET Comput. Digit. Tech., 3 (5): 487-500 (2009)Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning., , , , , и . ETS, стр. 1-2. IEEE, (2019)Experimental multiprocessor architecture dedicated for solving 3D PDEs., , , , , и . PDP, стр. 71-77. IEEE, (1993)IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system., , и . ETS, стр. 1-6. IEEE, (2016)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management., , , , , , , , , и 18 other автор(ы). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications., , , , , , , , , и . ESSCIRC, стр. 426-429. IEEE, (2008)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , и 18 other автор(ы). ISSCC, стр. 46-48. IEEE, (2020)