( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.

, , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Amann

K Dugaev

 

Другие публикации лиц с тем же именем

Instruction-based delay fault self-testing of pipelined processor cores., , , и . ISCAS (6), стр. 5686-5689. IEEE, (2005)Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , и . IEEE Trans. Computers, 58 (5): 692-705 (2009)Hypergraph Coloring and Reconfigured RAM Testing., и . IEEE Trans. Computers, 43 (6): 725-736 (1994)A Data Compression Technique for Built-In Self-Test., , и . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Routing TCP Flows in Underwater Mesh Networks., , и . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)Analysis and test procedures for NOR flash memory defects., и . Microelectron. Reliab., 48 (5): 698-709 (2008)Delay Fault Testing of Processor Cores in Functional Mode., , , и . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , и . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , и . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)A Tutorial on Built-In Self-Test, Part 2: Applications., , и . IEEE Des. Test Comput., 10 (2): 69-77 (1993)