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Disambiguation of "Kar, Gouri Sankar"

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Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT.

, , , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Svetlana Gourianova

Hari Sankar

Subramaniam Sankar

Catherine Gouriou

Nicolas Gourier

 

Other publications of authors with the same name

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs., , , , , and . IEEE Trans. Computers, 71 (9): 2219-2233 (2022)Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 733-746 (February 2023)Challenges and targets of MRAM-enabled scaled spintronic logic circuits., , , , , , , , , and 1 other author(s). CoRR, (2022)The Promise of 2-D Materials for Scaled Digital and Analog Applications., , , , , , , , , and 2 other author(s). ISSCC, page 394-395. IEEE, (2023)Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects., , , , , , , and . IRPS, page 1-6. IEEE, (2019)Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM., , , , , , , , , and 7 other author(s). VLSI Circuits, page 194-. IEEE, (2019)Doped GeSe materials for selector applications., , , , , , , , , and 1 other author(s). ESSDERC, page 168-171. IEEE, (2017)Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs., , , , , and . ITC, page 1-10. IEEE, (2020)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)Modeling and spectroscopy of ovonic threshold switching defects., , , , , , and . IRPS, page 1-5. IEEE, (2021)