Author of the publication

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2331-2335 (July 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs., , , and . ACM Trans. Design Autom. Electr. Syst., 28 (5): 76:1-76:26 (September 2023)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2331-2335 (July 2023)FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning., , , and . ISPD, page 93-101. ACM, (2024)A 3D Implementation of Convolutional Neural Network for Fast Inference., , , , , , , , , and . ISCAS, page 1-5. IEEE, (2023)RTL-to-GDS Design Tools for Monolithic 3D ICs., , , , , , , , , and . ICCAD, page 126:1-126:8. IEEE, (2020)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs., , , , and . ISPD, page 39-46. ACM, (2021)Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits., , , , , , , and . DAC, page 1-6. IEEE, (2023)