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Disambiguation of "Pentapati, Sai"

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Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2331-2335 (July 2023)

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Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sai Chang

 

Other publications of authors with the same name

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs., , , , , and . DATE, page 37-42. IEEE, (2020)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2331-2335 (July 2023)A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4575-4586 (2022)The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks., , and . ISPD, page 7-14. ACM, (2021)Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs., , , and . ISLPED, page 33:1-33:6. ACM, (2018)Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs., and . ISPD, page 127-134. ACM, (2022)On Legalization of Die Bonding Bumps and Pads for 3D ICs., , , , and . ISPD, page 62-70. ACM, (2023)Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs., , , , and . ISPD, page 39-46. ACM, (2021)Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs., , , , and . ISLPED, page 1-6. IEEE, (2019)GeoScaler: Geometry and Rendering-Aware Downsampling of 3D Mesh Textures., , , , and . CoRR, (2023)