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A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.

, , , , , , , , и . ISSCC, стр. 230-232. IEEE, (2012)

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Werner Böhr

Elisabeth Bohr

Horst Bohr

Kurt Bohr

Elke Böhr

 

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A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , и . ISSCC, стр. 376-377. IEEE, (2008)Silicon Trends and Limits for Advanced Microprocessors.. Commun. ACM, 41 (3): 80-87 (1998)The new era of scaling in an SoC world.. ISSCC, стр. 23-28. IEEE, (2009)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply., , , , , , , , и . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , и . ISSCC, стр. 456-457. IEEE, (2009)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , и . IEEE J. Solid State Circuits, 44 (1): 148-154 (2009)SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction., , , , , , , , и . IEEE J. Solid State Circuits, 40 (4): 895-901 (2005)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 324-606. IEEE, (2007)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , и . ISSCC, стр. 230-232. IEEE, (2012)CMOS Scaling Trends and Beyond., и . IEEE Micro, 37 (6): 20-29 (2017)