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Disambiguation of "Jiang, Hongwu"

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CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.

, , , and . MEMSYS, page 490-496. ACM, (2019)

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Hongwu Zhang

Jianzhong Jiang

Jiang Zhang

Andong Jiang

Minhua Jiang

 

Other publications of authors with the same name

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling., , , and . ESSCIRC, page 101-104. IEEE, (2022)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , and . CoRR, (2020)NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark., , , , and . Frontiers Artif. Intell., (2021)XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption., , , , and . ICCAD, page 77:1-77:6. IEEE, (2020)A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays., , , and . VLSI Technology and Circuits, page 266-267. IEEE, (2022)Architecture and Circuit Design Optimization for Compute-In-Memory.. Georgia Institute of Technology, Atlanta, GA, USA, (2023)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/70137).Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories., , , , and . DATE, page 1025-1030. IEEE, (2020)CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training., , , and . MEMSYS, page 490-496. ACM, (2019)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)