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LUT-Based Optimization For ASIC Design Flow.

, , , , , , , , и . DAC, стр. 871-876. IEEE, (2021)

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Vinícius Liebel

Vinícius Maran

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Exact Benchmark Circuits for Logic Synthesis., , , , , , и . IEEE Des. Test, 37 (3): 51-58 (2020)Transistor Count Optimization in IG FinFET Network Design., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)Unlocking fine-grain parallelism for AIG rewriting., , , , , и . ICCAD, стр. 87. ACM, (2018)Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation., , , , , и . SBCCI, стр. 1-6. IEEE, (2018)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , и . SBCCI, стр. 1-6. IEEE, (2012)Majority-based Design Flow for AQFP Superconducting Family., , , , , , , , , и 1 other автор(ы). DATE, стр. 34-39. IEEE, (2022)Transistor-level optimization of CMOS complex gates., , , , , и . LASCAS, стр. 1-4. IEEE, (2013)LUT-Based Optimization For ASIC Design Flow., , , , , , , , и . DAC, стр. 871-876. IEEE, (2021)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , и . SBCCI, стр. 41:1-41:6. ACM, (2014)