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LUT-Based Optimization For ASIC Design Flow.

L. Amarù, V. Possani, E. Testa, F. Marranghello, C. Casares, J. Luo, P. Vuillod, A. Mishchenko, and G. Micheli. DAC, page 871-876. IEEE, (2021)

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Patrick Pfeffer

Optimiertes Design kombinatorischer Verbindungsbibliotheken durch genetische Algorithmen und deren Bewertung anhand wissensbasierter Protein-Ligand-BindungsprofileP. Pfeffer. Uni Marburg, (2009)

Patrick Hansen

Entwicklung eines energetischen Sanierungsmodells für den europäischen Wohngebäudesektor unter dem Aspekt der Erstellung von Szenarien für Energie- und Co_1tn2-Einsparpotenziale bis 2030P. Hansen. Uni Siegen, (2009)

Patrick Muhl

Patrick Heinecke

Patrick Villwock

Other publications of authors with the same name

Scalable Boolean Methods in a Modern Synthesis Flow.E. Testa, L. Amarù, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P. Gaillardon, and G. Micheli. DATE, page 1643-1648. IEEE, (2019)Generalized matching from theory to application.P. Vuillod, L. Benini, and G. Micheli. ICCAD, page 13-20. IEEE Computer Society / ACM, (1997)Clock skew optimization for peak current reduction.P. Vuillod, L. Benini, A. Bogliolo, and G. Micheli. ISLPED, page 265-270. IEEE, (1996)Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.L. Benini, P. Vuillod, C. Jr., and G. Micheli. ISSS, page 57-. ACM / IEEE Computer Society, (1996)Integrated ESOP Refactoring for Industrial Designs.W. Haaswijk, L. Amarù, P. Vuillod, J. Luo, M. Soeken, and G. Micheli. ICECS, page 369-372. IEEE, (2018)SAT-Sweeping Enhanced for Logic Synthesis.L. Amarù, F. Marranghello, E. Testa, C. Casares, V. Possani, J. Luo, P. Vuillod, A. Mishchenko, and G. Micheli. DAC, page 1-6. IEEE, (2020)Improvements to boolean resynthesis.L. Amarù, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, J. Olson, R. Brayton, and G. Micheli. DATE, page 755-760. IEEE, (2018)Majority-based Design Flow for AQFP Superconducting Family.G. Meuli, V. Possani, R. Singh, S. Lee, A. Calvino, D. Marakkalage, P. Vuillod, L. Amarù, S. Chase, J. Kawa and 1 other author(s). DATE, page 34-39. IEEE, (2022)Re-mapping for low power under tight timing constraints.P. Vuillod, L. Benini, and G. Micheli. ISLPED, page 287-292. ACM, (1997)Improving LUT-based optimization for ASICs.W. Neto, L. Amarù, V. Possani, P. Vuillod, J. Luo, A. Mishchenko, and P. Gaillardon. DAC, page 421-426. ACM, (2022)

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Disambiguation of "Vuillod, Patrick"

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LUT-Based Optimization For ASIC Design Flow.

Please choose a person to relate this publication to

Patrick Pfeffer

Patrick Hansen

Patrick Muhl

Patrick Heinecke

Patrick Villwock

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vuillod, Patrick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML LUT-Based Optimization For ASIC Design Flow.

Please choose a person to relate this publication to

Patrick Pfeffer

Patrick Hansen

Patrick Muhl

Patrick Heinecke

Patrick Villwock

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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LUT-Based Optimization For ASIC Design Flow.