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A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design., , , и . ISPD, стр. 185-192. ACM, (2015)SwitchCraft: a framework for transistor network design., , , , , и . SBCCI, стр. 49-53. ACM, (2010)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5126-5130 (2022)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design., , , , , и . LATS, стр. 135-140. IEEE, (2016)Switch level optimization of digital CMOS gate networks., , , и . ISQED, стр. 324-329. IEEE Computer Society, (2009)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , и . LASCAS, стр. 227-230. IEEE, (2016)Improvements on the detection of false paths by using unateness and satisfiability., , , и . SBCCI, стр. 192-197. ACM, (2010)Area impact analysis of via-configurable regular fabric for digital integrated circuit design., , , , , и . SBCCI, стр. 103-108. ACM, (2011)KL-Cuts: A new approach for logic synthesis targeting multiple output blocks., , , и . DATE, стр. 777-782. IEEE Computer Society, (2010)