( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
LUT-Based Optimization For ASIC Design Flow.

, , , , , , , , и . DAC, стр. 871-876. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Estelle Jiongo

Jiong Tao

Jiong Tian

Jiong Zhou

Jiong Zhang

 

Другие публикации лиц с тем же именем

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems., , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (4): 427-437 (2007)LUT-Based Optimization For ASIC Design Flow., , , , , , , , и . DAC, стр. 871-876. IEEE, (2021)Improving LUT-based optimization for ASICs., , , , , , и . DAC, стр. 421-426. ACM, (2022)Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems., и . ICCAD, стр. 357-364. IEEE Computer Society, (2000)Logic optimization and synthesis: Trends and directions in industry., , , и . DATE, стр. 1303-1305. IEEE, (2017)Integrated ESOP Refactoring for Industrial Designs., , , , , и . ICECS, стр. 369-372. IEEE, (2018)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems., и . VLSI Design, стр. 369-375. IEEE Computer Society, (2003)Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors., , , и . ICCD, стр. 391-394. IEEE Computer Society, (2002)Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems., , и . ICCAD, стр. 30-38. IEEE Computer Society / ACM, (2003)