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Graph-Based Transistor Network Generation Method for Supergate Design.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)

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A comparative study of CMOS gates with minimum transistor stacks., , , , and . SBCCI, page 93-98. ACM, (2007)Evaluating Geometric Aspects of Non-Series-Parallel Cells., , and . SBCCI, page 16:1-16:6. ACM, (2015)A new general purpose line probe routing algorithm., , and . ICECS, page 658-661. IEEE, (2014)A Straightforward Methodology for QCA Circuits Design., , and . SBCCI, page 1-6. IEEE, (2020)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering., , , , and . ISQED, page 47-52. IEEE Computer Society, (2008)SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)A survey of path search algorithms for VLSI detailed routing., , and . ISCAS, page 1-4. IEEE, (2017)Libra: An Automatic Design Methodology for CMOS Complex Gates., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1345-1349 (2018)Efficient transistor-level design of CMOS gates., , , , , and . ACM Great Lakes Symposium on VLSI, page 191-196. ACM, (2013)