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Graph-Based Transistor Network Generation Method for Supergate Design.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)

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Efficient transistor-level design of CMOS gates., , , , , and . ACM Great Lakes Symposium on VLSI, page 191-196. ACM, (2013)Topological characteristics of logic networks generated by a graph-based methodology., , , , , and . LASCAS, page 343-346. IEEE, (2016)Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios., , , , and . MUE, page 95-100. IEEE Computer Society, (2011)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , and . SBCCI, page 41:1-41:6. ACM, (2014)Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions., , , and . ISCAS, page 1744-1748. IEEE, (2022)The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis., , , , and . ISCAS, page 1610-1614. IEEE, (2022)Evaluating Geometric Aspects of Non-Series-Parallel Cells., , and . SBCCI, page 16:1-16:6. ACM, (2015)A new general purpose line probe routing algorithm., , and . ICECS, page 658-661. IEEE, (2014)A Straightforward Methodology for QCA Circuits Design., , and . SBCCI, page 1-6. IEEE, (2020)SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)