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Improving Diagnosis Resolution and Performance at High Compression Ratios.

, , , , , и . ITC, стр. 1-8. IEEE, (2018)

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Krishna Saxena

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Krishna Moorthi

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Krishna Narasimhan

 

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A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures., , , , , , и . NATW, стр. 43-48. IEEE, (2015)Advancing test compression to the physical dimension., , , , , , , , и . ITC, стр. 1-10. IEEE, (2017)Improving Diagnosis Resolution and Performance at High Compression Ratios., , , , , и . ITC, стр. 1-8. IEEE, (2018)Low cost at-speed testing using On-Product Clock Generation compatible with test compression., , , , , , , , и . ITC, стр. 724-733. IEEE Computer Society, (2010)A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices., , и . VLSID, стр. 5-6. IEEE Computer Society, (2014)High throughput multiple device diagnosis system., , , , и . ITC, стр. 1-10. IEEE, (2017)Low Power Reduced Pin Count Test Methodology., , , , и . ATS, стр. 251-258. IEEE, (2007)PPA Optimization of Test Points in Automotive Designs., , , , , , , , и . ITC, стр. 204-212. IEEE, (2022)Efficient testing of hierarchical core-based SOCs., , , , , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2014)