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A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS.

, , , , , , , , и . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)

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Vasant Desai

Vasant Shah

Vasant Kashinath Saosapurkar

 

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Automated verification of temporal properties specified as state machines in VHDL., , и . Great Lakes Symposium on VLSI, стр. 100-105. IEEE Computer Society, (1995)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , и . VLSI Design, стр. 292-297. IEEE Computer Society, (2012)Abstraction of data path registers for multilevel verification of large circuits., , , и . Great Lakes Symposium on VLSI, стр. 11-14. IEEE, (1994)Verification of Circuits Described in VHDL through Extraction of Design Intent., , , и . VLSI Design, стр. 417-420. IEEE Computer Society, (1994)A Unified Framework for Design Validation and Manufacturing Test., , и . ITC, стр. 875-884. IEEE Computer Society, (1996)Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking., , , , , , , и . FMCAD, том 1166 из Lecture Notes in Computer Science, стр. 19-33. Springer, (1996)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , и . VLSI Design, стр. 252-257. IEEE Computer Society, (2010)Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors., , и . ICCD, стр. 532-537. IEEE Computer Society, (1995)Verification of transient response of linear analog circuits., , и . VTS, стр. 42-47. IEEE Computer Society, (1995)Coverage Estimation for Symbolic Model Checking., , , и . DAC, стр. 300-305. ACM Press, (1999)