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Disambiguation of "Zanoni, Enrico"

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Optimization of ESD protection structures suitable for BCD6 smart power technology.

, , , , , and . Microelectron. Reliab., 43 (9-11): 1589-1594 (2003)

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Zanoni Dias

Ivo Zanoni

Reto Giacomi Zanoni

Enrico Streit

Enrico Meier

 

Other publications of authors with the same name

Stress-induced instabilities of shunt paths in high efficiency MWT solar cells., , , , , , , , , and . IRPS, page 3. IEEE, (2015)Demonstration of Bilayer Gate Insulator for Improved Reliability in GaN-on-Si Vertical Transistors., , , , , , , , , and . IRPS, page 1-5. IEEE, (2020)On-Wafer Dynamic Operation of Power GaN-HEMTs: Degradation Processes Investigated by a Novel Experimental Approach., , , , , , , , , and . IRPS, page 1-5. IEEE, (2024)Degradation induced by 2-MeV alpha particles on AlGaN/GaN high electron mobility transistors., , , , , , and . Microelectron. Reliab., 46 (9-11): 1750-1753 (2006)Improving the reliability and safety of automotive electronics., and . IEEE Micro, 13 (1): 30-48 (1993)Role of Gate Hole Injection in Minimizing Substrate Coupling and Electron Trapping in AlGaN/GaN Power HEMTs., , , , and . IRPS, page 17. IEEE, (2024)Trapping induced parasitic effects in GaN-HEMT for power switching applications., , , , and . ICICDT, page 1-4. IEEE, (2015)Modeling of Substrate Noise Injected by Digital Libraries., , , , , , , and . ISQED, page 488-492. IEEE Computer Society, (2001)Charge Trapping in GaN Power Transistors: Challenges and Perspectives., , , , , , , , , and 1 other author(s). BCICTS, page 1-4. IEEE, (2021)Evidence for temperature-dependent buffer-induced trapping in GaN-on-silicon power transistors., , , , , , , , and . IRPS, page 2. IEEE, (2015)