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Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.

R. Oh, B. Lee, S. Shin, W. Bae, H. Choi, I. Song, Y. Lee, J. Choi, C. Kim, S. Jang, и J. Choi. VLSIC, стр. 1-2. IEEE, (2014)

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Song Song

Song Song

Song-Hak Song-Schreff

Song Gao

Peng Song

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Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.C. Lee, J. Lee, K. Kim, J. Heo, G. Cha, J. Baek, D. Moon, Y. Eom, T. Kim, H. Cho и 25 other автор(ы). A-SSCC, стр. 153-156. IEEE, (2017)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.J. Moon, H. Yoo, H. Choi, I. Park, S. Kang, J. Kim, H. Chung, K. Kim, D. Lee, K. Song и 7 other автор(ы). A-SSCC, стр. 139-142. IEEE, (2018)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon и 16 other автор(ы). VLSI Circuits, стр. 147-148. IEEE, (2018)17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.W. Yun, I. Song, H. Jeoung, H. Choi, S. Lee, J. Kim, C. Kim, J. Choi, S. Jang, и J. Choi. ISSCC, стр. 1-3. IEEE, (2015)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang und 27 andere Autor(en). ISSCC, Seite 390-391. IEEE, (2017)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin und 9 andere Autor(en). A-SSCC, Seite 169-172. IEEE, (2016)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.R. Oh, B. Lee, S. Shin, W. Bae, H. Choi, I. Song, Y. Lee, J. Choi, C. Kim, S. Jang und 1 andere Autor(en). VLSIC, Seite 1-2. IEEE, (2014)