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A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)

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Song Song

Song Song

Song-Hak Song-Schreff

Youwang Song

Jianzhong Song

 

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Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning., , , , , , , и . MICRO, стр. 372-385. IEEE, (2020)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , и 27 other автор(ы). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)LL-PCM: Low-Latency Phase Change Memory Architecture., , , , и . DAC, стр. 14. ACM, (2019)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications., , , , , , , , , и 21 other автор(ы). ISSCC, стр. 1-3. IEEE, (2022)In-DRAM near-data approximate acceleration for GPUs., , , , , и . PACT, стр. 34:1-34:14. ACM, (2018)ScalCore: Designing a core for voltage scalability., , , , , и . HPCA, стр. 681-693. IEEE Computer Society, (2016)A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 40-41. IEEE, (2012)