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Nanocomputing Block based Multi-Context FPGA., , and . ERSA, page 297-298. CSREA Press, (2009)Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design., and . ACM Great Lakes Symposium on VLSI, page 429-430. ACM, (2011)Low power magnetic flip-flop based on checkpointing and self-enable mechanism., , , , and . NEWCAS, page 1-4. IEEE, (2013)Emerging hybrid logic circuits based on non-volatile magnetic memories., , , , , and . NEWCAS, page 1-4. IEEE, (2013)A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1077-1081 (March 2024)Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 239-250 (2019)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks., , , , , and . CoRR, (2021)Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks., , , , , and . CODES+ISSS, page 13-14. IEEE, (2022)A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density., , , , , and . NVMSA, page 1-6. IEEE, (2021)