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An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.

, , , , , , , , , , , , and . ISSCC, page 206-208. IEEE, (2011)

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A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time., , , , , , , , and . ISSCC, page 434-436. IEEE, (2012)High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A novel single poly-silicon EEPROM using trench floating gate., , and . MTDT, page 35-37. IEEE Computer Society, (2005)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2011)Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (11): 2786-2795 (2015)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell., , , , , , , , , and 1 other author(s). ISSCC, page 136-137. IEEE, (2016)4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic., , , , , , , , , and 5 other author(s). ISSCC, page 84-86. IEEE, (2016)A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips., , , , , , , and . APCCAS, page 695-698. IEEE, (2014)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)