Author of the publication

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link.

, , , , , , and . ESSCIRC, page 475-478. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1735-1739 (2020)0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link., , , , , , and . ESSCIRC, page 475-478. IEEE, (2021)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , and . ESSCIRC, page 384-387. IEEE, (2015)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)Reference Spur Reduction Techniques for a Phase-Locked Loop., , , and . IEEE Access, (2019)6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS., , , and . ISSCC, page 124-126. IEEE, (2020)A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 150-151. IEEE, (2022)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS., , , , , , and . ISSCC, page 410-411. IEEE, (2023)A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop., , , , , , , , and . VLSI Circuits, page 94-. IEEE, (2019)