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Disambiguation of "Beigné, Edith"

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Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.

, , , , , and . PATMOS, page 199-206. IEEE, (2013)

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Edith Grüber

Edith Hinze

Edith Halpaus

Edith Machill

Edith Markowsky

 

Other publications of authors with the same name

Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee., , and . ISSCC, page 298-299. IEEE, (2018)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology., , , , , , and . VLSI-SoC, page 168-173. IEEE, (2013)Event-driven asynchronous voltage monitoring in energy harvesting platforms., , , and . NEWCAS, page 457-460. IEEE, (2012)An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process., , , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 336-346. Springer, (2009)Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications., , , and . SiPS, page 1-3. IEEE, (2021)Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols., , , , , , , and . ICECS, page 789-792. IEEE, (2018)AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation., , , and . ASYNC, page 86-97. IEEE Computer Society, (2006)Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee., , and . ISSCC, page 116-117. IEEE, (2018)An Asynchronous Power Aware and Adaptive NoC Based Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology., , , , , , , , , and . NANOARCH, page 131-137. ACM, (2018)