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A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.

A. Wang, B. Richards, D. Dabbelt, H. Mao, S. Bailey, J. Han, E. Chang, J. Dunn, E. Alon, and B. Nikolic. A-SSCC, page 305-308. IEEE, (2017)

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Angie Genenger

Bernd-Rüdiger Angierski

Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylationL. Wang. Uni Marburg, (2009)

Hanchun Wang

Other publications of authors with the same name

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.A. Wang, W. Bae, J. Han, S. Bailey, P. Rigge, O. Ocal, Z. Wang, K. Ramchandran, E. Alon, and B. Nikolic. ESSCIRC, page 322-325. IEEE, (2018)A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers.N. Kuo, B. Yang, C. Wu, L. Kong, A. Wang, M. Reiha, E. Alon, A. Niknejad, and B. Nikolic. A-SSCC, page 345-348. IEEE, (2014)A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.A. Wang, B. Richards, D. Dabbelt, H. Mao, S. Bailey, J. Han, E. Chang, J. Dunn, E. Alon, and B. Nikolic. A-SSCC, page 305-308. IEEE, (2017)ACED: a hardware library for generating DSP systems.A. Wang, P. Rigge, A. Izraelevitz, C. Markley, J. Bachrach, and B. Nikolic. DAC, page 61:1-61:6. ACM, (2018)A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.J. Han, E. Chang, S. Bailey, Z. Wang, W. Bae, A. Wang, N. Narevsky, A. Whitcombe, P. Lu, B. Nikolic and 1 other author(s). CICC, page 1-4. IEEE, (2019)A generator of memory-based, runtime-reconfigurable 2N3M5K FFT engines.A. Wang, J. Bachrach, and B. Nikolic. ICASSP, page 1016-1020. IEEE, (2016)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.S. Bailey, J. Han, P. Rigge, R. Lin, E. Chang, H. Mao, Z. Wang, C. Markley, A. Izraelevitz, A. Wang and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations.A. Izraelevitz, J. Koenig, P. Li, R. Lin, A. Wang, A. Magyar, D. Kim, C. Schmidt, C. Markley, J. Lawson and 1 other author(s). ICCAD, page 209-216. IEEE, (2017)

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Disambiguation of "Wang, Angie"

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A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.

Please choose a person to relate this publication to

Angie Genenger

Bernd-Rüdiger Angierski

Wang Wang

Linfang Wang

Hanchun Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Angie"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.

Please choose a person to relate this publication to

Angie Genenger

Bernd-Rüdiger Angierski

Wang Wang

Linfang Wang

Hanchun Wang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.