( en | de | ru )

 

Disambiguation of "Choi, Jung-Hwan"

Author of the publication

copydeleteadd this publication to your clipboard
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.

, , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 122-133 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

 

Other publications of authors with the same name

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A Spatial Correlation Model for Shadow Fading in Indoor Multipath Propagation., , , and . VTC Fall, page 1-6. IEEE, (2010)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus., , , , , , , , , and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , and 6 other author(s). VLSIC, page 182-. IEEE, (2015)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface., , , , , , , , and . IEEE J. Solid State Circuits, 53 (1): 144-154 (2018)17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 59 (10): 3307-3316 (October 2024)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)