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Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.

, , , , , , и . SLIP, стр. 3:1-3:5. ACM, (2022)

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Giuliano Ramadori

Naoum Sistovaris

Giuliano Gregori

Giuliano Borrelli

Giovanna Giuliano

 

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Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , и 4 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)., , , , , , и . SLIP, стр. 17-23. IEEE, (2021)Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper., , , , , , и . SLIP, стр. 3:1-3:5. ACM, (2022)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node., , , , , , , , , и 7 other автор(ы). VLSI Technology and Circuits, стр. 429-430. IEEE, (2022)Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-4. IEEE, (2023)Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route., , , , , , и . 3DIC, стр. 1-4. IEEE, (2019)Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits., , , , , , , , , и 7 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2024)