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Disambiguation of "Zografos, Odysseas"

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Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.

, , , , , , and . SLIP, page 3:1-3:5. ACM, (2022)

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Odysseas Kontovourkis

Vasileios Zografos

Odysseas Papapetrou

Evangelos Zografos

 

Other publications of authors with the same name

Area and routing efficiency of SWD circuits compared to advanced CMOS., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Majority Logic Synthesis for Spin Wave Technology., , , , and . DSD, page 691-694. IEEE Computer Society, (2014)Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5)., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network., , , , and . SLIP, page 1-7. IEEE, (2021)System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents., , , , and . IRPS, page 1-7. IEEE, (2022)Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm., , , , , and . IRPS, page 1-7. IEEE, (2021)Majority logic synthesis., , , , , and . ICCAD, page 79. ACM, (2018)Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper., , , , , , and . SLIP, page 3:1-3:5. ACM, (2022)Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation., , , , , , , , , and 7 other author(s). IRPS, page 1-6. IEEE, (2024)Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)., , , , , , and . DATE, page 133-138. IEEE, (2020)