( en | de | ru )

 

Disambiguation of "Breuil, Laurent"

Author of the publication

copydeleteadd this publication to your clipboard
Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance.

, , , , , , , , , and . IRPS, page 1-6. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wolfgang te Breuil

Laurent Ntahuga

Laurent Bartholdi

Thomas Laurent

Thomas Laurent

 

Other publications of authors with the same name

Understanding the memory window in 1T-FeFET memories: a depolarization field perspective., , , , , , , and . IMW, page 1-4. IEEE, (2021)Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND., , , , , , , and . IMW, page 1-4. IEEE, (2023)Gate Side Injection Operating Mode for 3D NAND Flash Memories., , , , , , , , and . IMW, page 1-4. IEEE, (2024)High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction., , , , , , , , and . IMW, page 1-4. IEEE, (2022)Enabling 3D NAND Trench Cells for Scaled Flash Memories., , , , , , , , and . IMW, page 1-4. IEEE, (2023)Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance., , , , , , , , , and . IRPS, page 1-6. IEEE, (2024)First demonstration of ferroelectric Si: HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application., , , , , , , , and . IMW, page 1-4. IEEE, (2021)Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations., , , , , , , , and . Microelectron. Reliab., 54 (9-10): 2258-2261 (2014)