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At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells., , , , , , , , и . IMW, стр. 1-4. IEEE, (2022)Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks., , , , , , , , , и . IRPS, стр. 12-1. IEEE, (2022)Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND., , , , , , , и . IMW, стр. 1-4. IEEE, (2023)Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS., и . Microelectron. Reliab., 48 (8-9): 1300-1305 (2008)Gate Side Injection Operating Mode for 3D NAND Flash Memories., , , , , , , , и . IMW, стр. 1-4. IEEE, (2024)Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations., , , , , , , , и . Microelectron. Reliab., 54 (9-10): 2258-2261 (2014)Reliability of Mo as Word Line Metal in 3D NAND., , , , , и . IRPS, стр. 1-6. IEEE, (2021)Impact of mechanical strain on wakeup of HfO2 ferroelectric memory., , , , , , , , и . IRPS, стр. 1-6. IEEE, (2021)Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND., , , , , , , , , и . IRPS, стр. 1-5. IEEE, (2024)Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance., , , , , , , , , и . IRPS, стр. 1-6. IEEE, (2024)