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An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , и 2 other автор(ы). CICC, стр. 283-286. IEEE, (2000)A High-Level Synthesis Method for Weakly Testable Data Paths., , , , и . Asian Test Symposium, стр. 40-45. IEEE Computer Society, (1998)A Capture-Safe Test Generation Scheme for At-Speed Scan Testing., , , , , , , , , и 1 other автор(ы). ETS, стр. 55-60. IEEE Computer Society, (2008)Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification., , , , , , , , и . ICCAD, стр. 52-58. IEEE Computer Society, (2008)Session 16 - Embedded memory., и . CICC, IEEE, (2008)A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment., , , , , , , и . ICCAD, стр. 97-104. ACM, (2009)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , и 1 other автор(ы). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO., , , , , , , , , и 1 other автор(ы). CICC, стр. 213-216. IEEE, (2001)