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A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

, , , , , , , and . ICCAD, page 97-104. ACM, (2009)

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ATREX : Design for Testability System for Mega Gate LSIs., , , , , and . Asian Test Symposium, page 126-. IEEE Computer Society, (1997)Test Roles in Diagnosis and Silicon Debug., , , , , , and . ATS, page 367. IEEE, (2007)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)Small Delay Fault Model for Intra-Gate Resistive Open Defects., , , , , , and . VTS, page 27-32. IEEE Computer Society, (2009)Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.. DFT, page 227. IEEE Computer Society, (2010)An Automatic Test Generation System for Large Scale Gate Arrays., , , , and . COMPCON, page 445-451. IEEE Computer Society, (1986)Post-BIST Fault Diagnosis for Multiple Faults., , , , , , and . IEICE Trans. Inf. Syst., 91-D (3): 771-775 (2008)At-Speed Testing with Timing Exceptions and Constraints-Case Studies., , , , , , , , , and . ATS, page 153-162. IEEE, (2006)ASIC CAD system based on hierarchical design-for-testability., , , and . ITC, page 404-409. IEEE Computer Society, (1990)A Capture-Safe Test Generation Scheme for At-Speed Scan Testing., , , , , , , , , and 1 other author(s). ETS, page 55-60. IEEE Computer Society, (2008)