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A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

, , , , , , , and . ICCAD, page 97-104. ACM, (2009)

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Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , and . ATS, page 43-48. IEEE, (2019)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (3): 499-512 (2016)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , and . PRDC, page 124-129. IEEE, (2019)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)