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Disambiguation of "Pravossoudovitch, Serge"

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A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.

, , , and . Great Lakes Symposium on VLSI, page 24-. IEEE Computer Society, (1999)

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Elena Sergeyev

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Other publications of authors with the same name

On hardware generation of random single input change test sequences., , , , and . ETW, page 117-123. IEEE Computer Society, (2001)Intra-Cell Defects Diagnosis., , , , , , and . J. Electron. Test., 30 (5): 541-555 (2014)A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , and . J. Electron. Test., 24 (4): 353-364 (2008)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Defect Analysis for Delay-Fault BIST in FPGAs., , , and . IOLTS, page 124-128. IEEE Computer Society, (2003)On Using Efficient Test Sequences for BIST., , , , and . VTS, page 145-152. IEEE Computer Society, (2002)Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs., , , , , and . VTS, page 361-368. IEEE Computer Society, (2007)