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Noise tolerant ternary weight deep neural networks for analog in-memory inference.

J. Doevenspeck, P. Vrancx, N. Laubeuf, A. Mallik, P. Debacker, D. Verkest, R. Lauwereins, and W. Dehaene. IJCNN, page 1-8. IEEE, (2021)

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Ilse Peters

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Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing.M. Caselli, I. Papistas, S. Cosemans, A. Mallik, P. Debacker, and D. Verkest. NEWCAS, page 1-4. IEEE, (2021)A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.I. Papistas, S. Cosemans, B. Rooseleer, J. Doevenspeck, M. Na, A. Mallik, P. Debacker, and D. Verkest. CICC, page 1-2. IEEE, (2021)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.K. Ueyoshi, I. Papistas, P. Houshmand, G. Sarda, V. Jain, M. Shi, Q. Zheng, J. Giraldo, P. Vrancx, J. Doevenspeck and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays.S. Subhechha, S. Cosemans, A. Belmonte, N. Rassoul, S. Sharifi, P. Debacker, D. Verkest, R. Delhougne, and G. Kar. IMW, page 1-4. IEEE, (2023)Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge.N. Murthy, P. Vrancx, N. Laubeuf, P. Debacker, F. Catthoor, and M. Verhelst. SEC, page 14-25. IEEE, (2022)Noise tolerant ternary weight deep neural networks for analog in-memory inference.J. Doevenspeck, P. Vrancx, N. Laubeuf, A. Mallik, P. Debacker, D. Verkest, R. Lauwereins, and W. Dehaene. IJCNN, page 1-8. IEEE, (2021)Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.Y. Lin, P. Debacker, D. Trivkovic, R. Kim, P. Raghavan, and D. Pan. ICCD, page 415-418. IEEE Computer Society, (2017)Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.G. Sarda, N. Shah, D. Bhattacharjee, P. Debacker, and M. Verhelst. CoRR, (2024)Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.G. Sarda, N. Shah, D. Bhattacharjee, P. Debacker, and M. Verhelst. IISWC, page 226-228. IEEE, (2023)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.T. Evenblij, C. Tenllado, M. Perumkunnil, F. Catthoor, S. Sakhare, P. Debacker, G. Kar, A. Furnémont, N. Bueno, and J. Pérez. ICCD, page 255-263. IEEE, (2019)

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Disambiguation of "Debacker, Peter"

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Noise tolerant ternary weight deep neural networks for analog in-memory inference.

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Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Ilse Peters

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BibSonomy

Disambiguation of "Debacker, Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Noise tolerant ternary weight deep neural networks for analog in-memory inference.

Please choose a person to relate this publication to

Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Ilse Peters

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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Noise tolerant ternary weight deep neural networks for analog in-memory inference.