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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. Taylor, and R. Dreslinski. VLSI Circuits, page 30-. IEEE, (2019)

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A Holistic Solution for Reliability of 3D Parallel Systems.J. Bagherzadeh, A. Amarnath, J. Tan, S. Pal, and R. Dreslinski. ACM J. Emerg. Technol. Comput. Syst., 18 (1): 23:1-23:27 (2022)R2D3: A Reliability Engine for 3D Parallel Systems.J. Bagherzadeh, A. Amarnath, J. Tan, S. Pal, and R. Dreslinski. DAC, page 1-6. IEEE, (2020)A carbon nanotube transistor based RISC-V processor using pass transistor logic.A. Amarnath, S. Feng, S. Pal, T. Ajayi, A. Rovinski, and R. Dreslinski. ISLPED, page 1-6. IEEE, (2017)A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.S. Pal, D. Park, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, C. Zhao, A. Amarnath, T. Wesley and 8 other author(s). VLSI Circuits, page 150-. IEEE, (2019)SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.S. Pal, A. Amarnath, S. Feng, M. O'Boyle, R. Dreslinski, and C. Dubach. MICRO, page 1005-1021. ACM, (2021)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.A. Amarnath, J. Bagherzadeh, J. Tan, and R. Dreslinski. ISLPED, page 1-6. IEEE, (2019)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)Sparse-TPU: adapting systolic arrays for sparse matrices.X. He, S. Pal, A. Amarnath, S. Feng, D. Park, A. Rovinski, H. Ye, K. Chen, R. Dreslinski, and T. Mudge. ICS, page 19:1-19:12. ACM, (2020)Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.S. Pal, S. Feng, D. Park, S. Kim, A. Amarnath, C. Yang, X. He, J. Beaumont, K. May, Y. Xiong and 10 other author(s). PACT, page 175-190. ACM, (2020)

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Disambiguation of "Amarnath, Aporva"

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

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Disambiguation of "Amarnath, Aporva"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.