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Pareto based Multi-objective Mapping IP Cores onto NoC Architectures., , и . APCCAS, стр. 331-334. IEEE, (2006)Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit., , , , и . ASICON, стр. 1-4. IEEE, (2019)Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality., , , , , , , , и . Remote. Sens., 12 (11): 1866 (2020)Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling., , , , , , и . IEEE Trans. Parallel Distributed Syst., 31 (9): 2201-2219 (2020)A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator., , , , , и . ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations., , , , , , , и . ACM Trans. Design Autom. Electr. Syst., 24 (2): 25:1-25:22 (2019)Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding., , , и . IEICE Electron. Express, 13 (6): 20160019 (2016)Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration., , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 345-350. ACM, (2020)A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis., , и . ICECS, стр. 766-769. IEEE, (2008)Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code., , , и . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)