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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1538-1545 (2015)

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FinFET based SRAM bitcell design for 32 nm node and below., , and . Microelectron. J., 42 (3): 520-526 (2011)A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization., , , , , , , , , and 1 other author(s). VLSIC, page 84-. IEEE, (2015)SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1538-1545 (2015)BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit., , , , , , , and . ISQED, page 87-91. IEEE, (2010)15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications., , , , , , , , , and 2 other author(s). ISSCC, page 238-240. IEEE, (2020)Technology-design-manufacturing co-optimization for advanced mobile SoCs.. CICC, page 1-8. IEEE, (2014)-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Holistic technology optimization and key enablers for 7nm mobile SoC., , , , , , , , , and 4 other author(s). VLSIC, page 198-. IEEE, (2015)Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)