( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

, , , , , , , , , и . FPGA, стр. 1-12. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Zhiru Shi

Zhang Zhang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Yue Zhang

Wei Zhang

 

Другие публикации лиц с тем же именем

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (11): 1817-1830 (2017)Architecture and synthesis for multi-cycle on-chip communication., , , , и . CODES+ISSS, стр. 77-78. ACM, (2003)GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding., , , , и . ICLR, OpenReview.net, (2020)Enabling adaptive loop pipelining in high-level synthesis., , , и . ACSSC, стр. 131-135. IEEE, (2017)Special Session: Machine Learning for Embedded System Design., , , , , , , , , и 1 other автор(ы). CODES+ISSS, стр. 28-37. IEEE, (2023)An efficient and versatile scheduling algorithm based on SDC formulation., и . DAC, стр. 433-438. ACM, (2006)A reconfigurable analog substrate for highly efficient maximum flow computation., и . DAC, стр. 17:1-17:6. ACM, (2015)Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks., , , , , и . ASP-DAC, стр. 152-157. ACM, (2021)PokeBNN: A Binary Pursuit of Lightweight Accuracy., , и . CVPR, стр. 12465-12475. IEEE, (2022)High-level synthesis with timing-sensitive information flow enforcement., , , и . ICCAD, стр. 88. ACM, (2018)