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Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)Pareto based Multi-objective Mapping IP Cores onto NoC Architectures., , and . APCCAS, page 331-334. IEEE, (2006)Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit., , , , and . ASICON, page 1-4. IEEE, (2019)Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 345-350. ACM, (2020)A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator., , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (2): 25:1-25:22 (2019)Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling., , , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2201-2219 (2020)Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding., , , and . IEICE Electron. Express, 13 (6): 20160019 (2016)Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality., , , , , , , , and . Remote. Sens., 12 (11): 1866 (2020)A Mapping Method for Reconfigurable Array based on Decoupled DataFlow., , , , , and . BigDataSecurity, page 180-185. IEEE, (2021)