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Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (2): 109-130 (2002)

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Testing redundant asynchronous circuits by variable phase splitting., , and . EURO-DAC, page 328-333. IEEE Computer Society, (1994)Solving the State Assignment Problem for Signal Transition Graphs., , , and . DAC, page 568-572. IEEE Computer Society Press, (1992)Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool., , , and . DAC, page 254-260. ACM Press, (1995)Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems., , and . IEEE Des. Test Comput., 22 (1): 28-38 (2005)Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework., , , and . J. Electronic Imaging, 23 (5): 053012 (2014)A software development tool chain for a reconfigurable processor., , and . CASES, page 93-98. ACM, (2001)Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis., , , and . IEEE Access, (2017)Designing parameterized signal processing ips for high level synthesis in a model based design environment., and . CODES+ISSS, page 295-304. ACM, (2012)Enabling adaptability through elastic clocks., , and . DAC, page 8-10. ACM, (2009)A Fully-Automated Desynchronization Flow for Synchronous Circuits., , , and . DAC, page 982-985. IEEE, (2007)