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An ATE assisted DFD technique for volume diagnosis of scan chains., , , and . DAC, page 31:1-31:6. ACM, (2013)Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure., , and . ISCAS, page 1-5. IEEE, (2019)An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design., and . RAIT, page 543-548. IEEE, (2016)Confidence Based Power Aware Testing., , , and . ISED, page 62-66. IEEE, (2012)Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach., , , , , and . ICIT, page 228-233. IEEE, (2019)Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization., , and . ISED, page 172-176. IEEE, (2012)Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling., and . Integr., (2015)Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution., , and . Integr., (2018)Reliability-aware application mapping onto mesh based Network-on-Chip., , and . Integr., (2018)Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing., , and . Integr., 45 (2): 211-221 (2012)