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3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps., , , , , , , , , and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges., , , , , , , and . 3DIC, page 1-7. IEEE, (2014)Stress mitigation of 3D-stacking/packaging induced stresses., , , , , , , , and . IRPS, page 4. IEEE, (2018)Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications., , , , , , , , and . IRPS, page 1-4. IEEE, (2019)Fine grain thermal modeling and experimental validation of 3D-ICs., , , , , , , , , and . Microelectron. J., 42 (4): 572-578 (2011)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)Towards accurate temperature prediction in BEOL for reliability assessment (Invited)., , , , , , , , , and 1 other author(s). IRPS, page 1-7. IEEE, (2023)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Thermal experimental and modeling analysis of high power 3D packages., , , , , and . ICICDT, page 1-4. IEEE, (2015)