Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A-QED Verification of Hardware Accelerators., , , , , , , , , and 3 other author(s). DAC, page 1-6. IEEE, (2020)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)The Sparse Abstract Machine., , , , , , , and . CoRR, (2022)Compiling Halide Programs to Push-Memory Accelerators., , , , , , , , , and 1 other author(s). CoRR, (2021)Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform., , , and . FPGA, page 239-248. ACM, (2018)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Automating System Configuration., , , , , , and . FMCAD, page 102-111. IEEE, (2021)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration., , , , , , , , , and 13 other author(s). HCS, page 1-30. IEEE, (2022)Accelerating Large-Scale Graph Analytics with FPGA and HMC., , , and . FCCM, page 82. IEEE Computer Society, (2017)