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Disambiguation of "da Rosa Jr., Leomar S."

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NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.

, , , , , and . SBCCI, page 1-6. IEEE, (2012)

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Catarina Caetano da Rosa

Foued Jrad

Da Liu

Da Wang

Robert Jr Cramer

 

Other publications of authors with the same name

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms., , , , , and . ACM Great Lakes Symposium on VLSI, page 407-410. ACM, (2008)DAG based library-free technology mapping., , , , and . ACM Great Lakes Symposium on VLSI, page 293-298. ACM, (2007)Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)Improving the methodology to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2013)A comparative study of CMOS gates with minimum transistor stacks., , , , and . SBCCI, page 93-98. ACM, (2007)The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits., , , , and . ICECS, page 433-436. IEEE, (2018)Fast disjoint transistor networks from BDDs., , , , , and . SBCCI, page 137-142. ACM, (2006)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering., , , , and . ISQED, page 47-52. IEEE Computer Society, (2008)Post-processing of supergate networks aiming cell layout optimization., , , , , , and . ISCAS, page 1-4. IEEE, (2017)